module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    parameter IDLE = 2'd0;
    parameter FIRST = 2'd1;
    parameter SECOND = 2'd2;
    
    reg	[1:0]	state;
    reg	[1:0]	next_state;
    
    always @(posedge clk or negedge aresetn) begin
        if(!aresetn) begin
            state <= IDLE;
        end
        else begin
            state <= next_state;
        end
    end
    
    always @(*) begin
        case(state)
            IDLE:	next_state = x ? FIRST : IDLE;
            FIRST:	next_state = x ? FIRST : SECOND;
            SECOND:	next_state = x ? FIRST : IDLE;
        endcase
    end
    
    assign z = ((state == SECOND) && x);
    
endmodule
